王雪岩查看源代码讨论查看历史
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王雪岩，女，北京航空航天大学讲师。
人物简历
教育经历
[1].2013.9 -- 2018.7 清华大学 计算机科学与技术 博士研究生毕业 工学博士学位
[2].2015.2 -- 2016.2 University of Maryland, College Park 电子与计算机工程 其他 无
[3].2009.9 -- 2013.7 山东大学 计算机科学与技术 大学本科毕业 工学学士学位
工作经历
[1].2021.10 -- 至今 北京航空航天大学 集成电路科学与工程学院 助理教授
[2].2018.11 -- 2021.10 北京航空航天大学 集成电路科学与工程学院 “卓越百人”博士后
研究方向
[1] 软硬件协同加速设计
[2] 存算一体架构与芯片设计
[3] 图计算/图神经网络
科研项目
[1] 国家自然科学基金项目青年项目 2021.01-2023.12 主持
[2] 教育部产学合作协同育人项目 2022.08-2024.8 主持
[3] 中科院计算所计算机体系结构国家重点实验室开放课题 2020.01-2022.12 主持
学术成果
论文
Y. Wei, X. Wang, S. Zhang, J. Yang, X. Jia, Z. Wang, G. Qu, W. Zhao, "IMGA: Efficient In-Memory Graph Convolution Network Aggregation with Data Flow Optimizations", in IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), doi: 10.1109/TCAD.2023.3288509. (通讯作者，CCF A类期刊)
X. Chen, X. Wang, X. Jia, J. Yang, G. Qu, W. Zhao, "Accelerating Graph Connected Component Computation with Emerging Processing-In-Memory Architecture", in IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), 41(12): 5333-5342, 2022. (通讯作者，CCF A类期刊)
L. Yue, H. Zhang, X. Wang, H. Cai, Y. Zhang, S. Lv, R. Liu, W. Zhao, "Toward Energy-Efficient Sparse Matrix-Vector Multiplication with Near STT-MRAM Computing Architecture," 2023 28th Asia and South Pacific Design Automation Conference (ASP-DAC), Tokyo, Japan, 2023, pp. 222-227. (通讯作者，EDA领域著名会议)
X. Wang, J. Yang, Y. Zhao, X. Jia, R. Yin, X. Chen, G. Qu, W. Zhao, "Triangle Counting Accelerations: From Algorithm to In-Memory Computing Architecture," in IEEE Transactions on Computers (TC), 71(10): 2462-2472, 2022. (CCF A类期刊)
X. Wang, J. Yang, Y. Zhao, Y. Qi, M. Liu, X. Cheng, X. Jia, X. Chen, G. Qu, and W. Zhao. Tcim: Triangle counting acceleration with processing-in-mram architecture. In 2020 57th ACM/IEEE Design Automation Conference (DAC), pages 1–6. IEEE, 2020. (CCF A 类，EDA领域最高会议，获得“最佳论文候选”)
X. Wang, Q. Zhou, Y. Cai, and G. Qu. Toward a formal and quantitative evaluation framework for circuit obfuscation methods. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), 38(10):1844–1857, 2019. (CCF A类期刊)
X. Wang, J. Yang, Y. Zhao, X. Jia, G. Qu, and W. Zhao. Hardware security in spin-based computing-in-memory: Analysis, exploits, and mitigation techniques. ACM Journal on Emerging Technologies in Computing Systems (JETC), 16(4):1–18, 2020.
X. Wang, Q. Zhou, Y. Cai, and G. Qu. Parallelizing sat-based de-camouflaging attacks by circuit partitioning and conflict avoiding. Integration, 67:108–120, 2019.
X. Wang, Q. Zhou, Y. Cai, and G. Qu. A conflict-free approach for parallelizing sat-based de-camouflaging attacks. In 2018 23rd Asia and South Pacific Design Automation Conference (ASP-DAC), pages 259–264. IEEE, 2018. (接收率：32%)
X. Wang, Q. Zhou, Y. Cai, and G. Qu. Spear and shield: Evolution of integrated circuit camouflaging. Journal of Computer Science and Technology (JCST), 33(1):42–57, 2018. (CCF B类期刊)
X. Wang, M. Gao, Q. Zhou, Y. Cai, and G. Qu. Gate camouflaging-based obfuscation. In Hardware Protection through Obfuscation, pages 89–102. Springer, 2017. (专著)
X. Wang, Q. Zhou, Y. Cai, and G. Qu. An empirical study on gate camouflaging methods against circuit partition attack. In Proceedings of the on Great Lakes Symposium on VLSI (GLSVLSI), pages 345–350, 2017. (接收率：24%)
X. Wang, Y. Cai, and Q. Zhou. Cell spreading optimization for force-directed global placers. In 2017 IEEE International Symposium on Circuits and Systems (ISCAS), pages 1–4. IEEE, 2017.
X. Wang, X. Jia, Q. Zhou, Y. Cai, J. Yang, M. Gao, and G. Qu. Secure and low-overhead circuit obfuscation technique with multiplexers. In 2016 International Great Lakes Symposium on VLSI (GLSVLSI), pages 133–136. IEEE, 2016. (接收率：25%)
X. Wang,, Q. Zhou, Y. Cai, and G. Qu. Is the secure ic camouflaging really secure? In 2016 IEEE International Symposium on Circuits and Systems (ISCAS), pages 1710–1713. IEEE, 2016.
X. Jia, H. Gu, Y. Liu, J. Yang, X. Wang, W. Pan, Y. Zhang, S. D. Cotofana, and W. Zhao, An Energy-Efficient Bayesian Neural Network Implementation Using Stochastic Computing Method, in IEEE Transactions on Neural Networks and Learning Systems (TNNLS), doi: 10.1109/TNNLS.2023.3265533.
X. Jia, J. Yang, R. Liu, X. Wang, S. D. Cotofana, and W. Zhao. Efficient computation reduction in bayesian neural networks through feature decomposition and memorization. IEEE transactions on neural networks and learning systems (TNNLS), 32(4):1703–1712, 2020.
Y. Pan, X. Jia, Z. Cheng, P. Ouyang, X. Wang, J. Yang, and W. Zhao. An stt-mram based reconfigurable computing-in-memory architecture for general purpose computing. CCF Transactions on High Performance Computing, 2(3):272–281, 2020.
Y. Zhao, J. Yang, X. Jia, X. Wang, Z. Wang, W. Kang, Y. Zhang, and W. Zhao. Exploiting near-memory processing architectures for bayesian neural networks acceleration. In 2019 IEEE Computer Society Annual Symposium on VLSI (ISVLSI), pages 203–206. IEEE, 2019.
J. Yang, X. Wang, Q. Zhou, Z. Wang, H. Li, Y. Chen, and W. Zhao. Exploiting spin-orbit torque devices as reconfigurable logic for circuit obfuscation. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), 38(1):57–69, 2018.
S. Jiang, N. Xu, X. Wang, and Q. Zhou. An efficient technique to reverse engineer minterm protection based camouflaged circuit. Journal of Computer Science and Technology (JCST), 33(5):998–1006, 2018.
Q. Zhou, X. Wang, Z. Qi, Z. Chen, Q. Zhou, and Y. Cai. An accurate detailed routing routability prediction model in placement. In 2015 6th Asia Symposium on Quality Electronic Design (ASQED), pages 119–122. IEEE, 2015.[1]